1. Field of the Invention
The present invention generally relates to charge transfer devices and, more particularly, to a charge transfer device having a charge transfer register.
2. Description of the Prior Art
In general, a charge transfer device such as a charge-coupled device (CCD) or the like has a charge transfer region called a register formed on the chip thereof. The register is composed of a plurality of transfer electrodes arrayed to control the potential and a channel region serving as a charge transfer path formed on the under part of the transfer electrodes.
A CCD solid state image sensing device is realized by the addition of a sensor (photosensing section) which carries out the photoelectric-conversion to the above-mentioned charge transfer function. Particularly in the color solid state image sensing device, different color light transmission filters are formed and sensors corresponding to respective colors are provided. In a color linear sensor, for example, sensor section of one row or sensor sections of a plurality of rows are formed and signal is output at every color. In a color solid state image sensing device in which sensors corresponding to respective colors are sequentially arrayed, a register is provided in parallel to the sensor array. Then, signals of respective colors are transferred from the sensor section to the register one at a time and color signals are sequentially read out from the register in a distributed fashion and in the output order. Further, in a color solid state image sensing device having a plurality of sensor section arrays, a register is provided at every sensor array and respective color signals are output from the respective registers.
Also, the number of register in the charge transfer device is not limited to one and the charge transfer device includes a plurality of registers frequently. In the case of the color linear sensor, for example, a plurality of registers corresponding to respective colors are arranged in parallel to the sensor array in which sensors corresponding to respective colors are sequentially arrayed.
It is frequently observed that the above-mentioned register is driven by a four-phase driving system. In this case, in a register section 1, as shown in FIG. 1, a plurality of transfer electrodes 6 are arrayed on a channel region 4 of a first conductivity type, i.e., N type through a gate insulating layer 5 along the charge transfer direction shown by an arrow a and four transfer sections SR (SR.sub.1, S.sub.2, SR.sub.3, SR.sub.4), each having the transfer electrode 6 are formed as one bit to which four-phase drive pulses .PHI..sub.1,.PHI..sub.2, .PHI..sub.3 and .PHI..sub.4 are applied, respectively. The four-phase drive pulses .PHI..sub.1, .PHI..sub.2, .PHI..sub.3 and .PHI..sub.4 are formed of clock pulses of the same waveform as shown in FIG. 2. In FIG. 1, reference numeral 2 depicts a semiconductor substrate of a first conductivity such as N type and 3 depicts a well region of a second conductivity type such as P type.
In the conventional register driven by the four-phase drive system, as shown in FIG. 2, a signal charge is transferred from the first transfer section SR.sub.1 to th second transfer section SR.sub.2 during the interval from time t.sub.0 to time t.sub.2, transferred from the second transfer section SR.sub.2 to the third transfer section SR.sub.3 during the interval from time t.sub.2 to time t.sub.4, transferred from the third transfer section SR.sub.3 to the fourth transfer section SR.sub.4 during the interval from time t.sub.4 to time t.sub.6 and transferred from the fourth transfer section SR.sub.4 to the first transfer section SR.sub.1 during the interval from time t.sub.6 to t.sub.8, thereby one-bit transfer being effected. Accordingly, one cycle of the clock pulse for transferring the electric charge in a one-bit transfer fashion lies in a range of from t.sub.0 to t.sub.8. In the register of the charge transfer device, however, in order to reduce the transfer time, it is desired that a so-called data rate is increased more.